Patent Document 1 discloses an example of a technique to generate a multi-phase clock signal by using a PLL circuit. A configuration of the PLL circuit disclosed in Patent Document 1 will be explained with reference to FIG. 15. As shown in FIG. 15, a PLL circuit 1000 disclosed in Patent Document 1 includes a phase frequency comparator 1001, a charge pump 1002, a low pass filter 1003, a voltage controlled oscillator 1004, and a delay circuit 1005.
The voltage controlled oscillator 1004 oscillates at a frequency in accordance with a controlled voltage and generates an output clock signal. The phase frequency comparator 1001 compares the phase of the output clock signal generated by the voltage controlled oscillator 1004 with the phase of an input clock signal and generates an error signal in accordance with the phase difference. The error signal is integrated by the charge pump 1002 and the low pass filter 1003 and applied to the voltage controlled oscillator 1004 as the controlled voltage.
The delay circuit 1005 includes a plurality of differential buffers and outputs a multi-phase output clock signal by delaying the input clock signal in accordance with the controlled voltage.
As described above, in the PLL circuit, the voltage controlled oscillator is arranged so as to oscillate in accordance with the frequency and the phase of the input clock signal. In this situation, in a case where a clock signal having a frequency that is lower than an operation frequency range of the PLL circuit is input or in a case where the clock signal is stopped, in other words, in a case where the clock signal is fixed so as to be at a high level or a low level, the voltage controlled oscillator stops oscillating because the PLL circuit follows the frequency of the clock signal. However, even while the voltage controlled oscillator is being stopped, generally speaking, electric current is constantly flowing in the analog circuits, such as the phase frequency comparator, the charge pump, and the like, that are included in the PLL circuit. As a result, electric power is consumed wastefully.
To cope with this situation, a PLL circuit has been developed so as to operate intermittently in order to keep the electric power consumption of the PLL circuit itself low. More specifically, when the PLL circuit is not in use, the PLL circuit is put into a sleep (OFF) state so that no electric current is flowing in the analog circuits included in the PLL circuit. Only when the PLL circuit is in use, the PLL circuit is changed into an operation (ON) state from the sleep state.
To the PLL circuit 1000 shown in FIG. 16, a PLL power down signal that puts the PLL circuit 1000 into the sleep state is input from the outside thereof, so that the PLL power down signal is input to the phase frequency comparator 1001, the charge pump 1002, and the voltage controlled oscillator 1004. The phase frequency comparator 1001, the charge pump 1002, and the voltage controlled oscillator 1004 stop operating when the PLL power down signal becomes active.
Patent Document 1: International Publication No. WO00/65717